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Understand why data structures matter through memory systems
Section 2 of 4
Discover how memory access patterns can make the difference between milliseconds and minutes in program execution.
Latency: 1-3 CPU cycles (approx. 0.5 nanoseconds)
When: Data is already in L1/L2 cache
Reason: Spatial Locality (adjacent data loaded together)
Latency: ~200 CPU cycles (approx. 100 nanoseconds)
When: Data must be fetched from Main Memory (RAM)
Impact: CPU stalls while waiting for data
Latency: Millions of CPU cycles (milliseconds)
When: Data is on SSD/HDD (Virtual Memory/Page Fault)
Analogy: Like waiting for a package cross-country vs reaching for your desk